Why India believes a 3D glass semiconductor project is its most important chip bet

India is backing an indigenously relevant 3D glass semiconductor packaging technology, with its first advanced 3D chip packaging unit being established in Bh...

What Happened

India is backing an indigenously relevant 3D glass semiconductor packaging technology, with its first advanced 3D chip packaging unit being established in Bhubaneswar, Odisha — India's first facility of this kind.
The project involves 3D glass-substrate-based heterogeneous integration: stacking multiple chips on glass substrates rather than conventional silicon interposers, which allows for denser, more power-efficient chip assemblies suited to AI and high-performance computing workloads.
The Odisha facility, with a proposed investment of approximately ₹1,943 crore, is expected to produce 70,000 glass panels annually and begin commercial production by August 2028, with full-scale operations by 2030.
The project is one of four semiconductor projects approved under the India Semiconductor Mission (ISM) in August 2025, reflecting a strategic choice to target advanced packaging — a segment where India can compete without attempting to match Taiwan's or South Korea's dominance in front-end chip fabrication.
A Bengaluru-based startup connection to the technology highlights India's ambition to develop domestic intellectual property in the semiconductor packaging space, rather than purely hosting foreign-designed fabs.

Static Topic Bridges

India Semiconductor Mission — Policy Framework and Rationale

The India Semiconductor Mission (ISM) was launched in 2021 under the Ministry of Electronics and Information Technology (MeitY), with a total financial outlay of ₹76,000 crore. Its central aim is to build a domestic semiconductor and display manufacturing ecosystem, reducing India's near-total dependence on chip imports — a strategic vulnerability exposed sharply by the global chip shortage of 2020–2023.

ISM launched: 2021; nodal ministry: MeitY (Ministry of Electronics and Information Technology)
Total outlay: ₹76,000 crore (Phase 1); ISM 2.0 launched April 2025 with ₹22,919 crore (later raised to ₹40,000 crore)
Central government incentive: up to 50% of project cost covered for approved semiconductor fab units; state governments provide additional support (land, utilities, incentives)
As of late 2025: 10 semiconductor projects across 6 states approved; total investment commitments exceeding ₹1.6 lakh crore (~$18–19 billion)
ISM's three-track approach:
Semiconductor fabrication (front-end fabs — most capital-intensive; none yet at leading-edge nodes)
Display manufacturing (fab)
Assembly, Testing, Marking, and Packaging (ATMP) — more immediately achievable; India's primary near-term entry point
ISM 2.0 focus: semiconductor equipment and materials manufacturing; full-stack Indian semiconductor IP development; supply chain fortification

Connection to this news: The 3D glass semiconductor packaging unit is an ATMP project under ISM, representing India's strategic choice to enter the semiconductor value chain through advanced packaging rather than front-end fabrication — a technically feasible and strategically rational pathway.

Semiconductor Packaging — Technology Landscape and India's Advantage

Semiconductor packaging is the process of encasing a bare chip (die) in a protective housing and connecting it to a circuit board or system. Traditionally, packaging was considered a low-value, labour-intensive activity, but "advanced packaging" — encompassing 3D stacking, heterogeneous integration, chiplets, and glass substrates — has emerged as a critical differentiator for AI chips and high-performance computing.

Conventional packaging (2D): Single chip in a flat package; mature technology; commodity market dominated by Malaysia, China, Thailand.
Advanced packaging (2.5D/3D):
2.5D: Multiple chips placed side-by-side on a silicon interposer (intermediate layer); used in GPU-HBM memory stacks (e.g., NVIDIA H100).
3D stacking: Chips stacked vertically with through-silicon vias (TSVs) or hybrid bonding; highest performance density.
Glass substrates: Replacing silicon interposers with glass — superior electrical insulation, thermal stability, and scalability for larger panels; enables cost-effective high-density chip integration.
Why glass over silicon: Glass allows larger panel sizes (reducing cost per unit), has better RF signal integrity, and is thermally stable — critical for AI accelerator chips running at high power densities.
Market significance: Advanced packaging is projected to be a $60+ billion global market by 2030, with demand driven by AI hardware (GPUs, NPUs, HBM memory).
Global leaders: TSMC (Taiwan) dominates advanced packaging with CoWoS and SoIC technologies; ASE Group, Amkor, and Samsung lead in conventional ATMP.
India's gap: India currently has minimal presence in even conventional packaging; the Odisha facility will be India's first advanced 3D packaging facility.

Connection to this news: By choosing glass-substrate 3D packaging — a nascent but high-growth technology segment — India avoids direct competition with established TSMC-led silicon interposer packaging while positioning itself in a market where the technology standards are still being set, giving domestic developers a chance to build early IP.

Chiplet Architecture and Heterogeneous Integration — Why This Matters

The semiconductor industry's transition from monolithic chips (single large die) to chiplet-based designs (multiple smaller dies integrated in a package) is driving a revolution in how chips are designed, manufactured, and packaged. This architectural shift makes advanced packaging a first-order competitive factor rather than a commodity afterthought.

Chiplet: A small, modular silicon die designed to be integrated with other chiplets in a single package, rather than building everything on one large monolithic chip. Example: AMD's EPYC and Ryzen processors use chiplets.
Heterogeneous integration: Combining chiplets made by different manufacturers, on different process nodes, or of different types (logic, memory, analog) in a single package — enabled by advanced packaging technologies.
India's relevance: Chiplets allow fabless design companies to develop specialised chips without owning a fab; India's strong semiconductor design ecosystem (30+ global chip companies have design centres in India) makes chiplet-based heterogeneous integration particularly relevant.
India has an estimated 20% share of the global semiconductor design workforce, making chip design — not fabrication — its established strength.
The government's Chips to Startup (C2S) programme (under MeitY) aims to train 85,000 engineers in chip design by 2025, building on this existing strength.

Connection to this news: The 3D glass packaging project is the physical manufacturing complement to India's existing chip design strength — if Indian designers can produce chiplet designs and domestic packaging facilities can integrate them, India gains a closed-loop capability that does not require dependence on Taiwanese or Korean packaging houses.

Global Semiconductor Supply Chain — Geopolitical Dimension

The global semiconductor industry is characterised by extreme geographic concentration: over 90% of advanced logic chips are fabricated by TSMC in Taiwan; packaging and testing are dominated by a handful of Asian hubs. This concentration has become a major geopolitical concern, accelerating semiconductor diversification investments by the US, EU, India, and Japan.

CHIPS and Science Act (USA, 2022): $52.8 billion in subsidies for US semiconductor manufacturing and R&D; designed to reduce dependence on Taiwan.
European Chips Act (2023): €43 billion to double Europe's semiconductor market share to 20% by 2030.
Taiwan's strategic vulnerability: Taiwan produces ~60% of the world's semiconductors and over 90% of the most advanced chips (sub-5 nm); its geopolitical situation vis-à-vis China makes supply chain diversification a global strategic priority.
India's semiconductor import dependency: India imports nearly all its chips, spending ~$24 billion annually on semiconductor imports (as of 2023-24), with demand projected to reach $100 billion by 2030.
"China+1" strategy: Global manufacturers diversifying supply chains beyond China — India, Vietnam, and Malaysia are primary beneficiaries.
AUKUS and Quad semiconductor initiatives: Technology supply chain resilience is a key agenda item in both groupings, with semiconductor cooperation a priority for India-US technology partnerships.

Connection to this news: India's semiconductor investments — including the Odisha 3D packaging facility — are explicitly motivated by supply chain resilience objectives, not just industrial policy. The government's strategic framing of this as India's "most important chip bet" reflects the broader geopolitical logic of semiconductor self-reliance.

Key Facts & Data

India Semiconductor Mission (ISM) outlay: ₹76,000 crore (Phase 1, 2021); ISM 2.0: ₹40,000 crore (April 2025)
Nodal ministry: MeitY (Ministry of Electronics and Information Technology)
Projects approved under ISM (as of late 2025): 10 projects across 6 states; investment commitments: ₹1.6 lakh crore+
Odisha 3D packaging facility investment: ~₹1,943 crore; production capacity: 70,000 glass panels/year; 50 million assembled units; commercial production target: August 2028
India's semiconductor import spend: ~$24 billion/year (2023-24); projected demand: $100 billion by 2030
India's share of global semiconductor design workforce: ~20%
Chips to Startup (C2S) programme target: 85,000 chip design engineers trained by 2025
US CHIPS Act: $52.8 billion (2022); EU Chips Act: €43 billion (2023)
TSMC's market share in advanced chip fabrication (sub-5 nm): >90%
Advanced packaging global market projection: $60+ billion by 2030
Advanced packaging types: 2.5D (silicon interposer), 3D (TSV/hybrid bonding), glass substrate (emerging)
ISM government incentive: up to 50% of approved project cost covered by the Centre