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Government takes steps to train 85,000 chip designers in 315 institutions

March 07, 2026 4 min read Science & Technology Economics GS Paper 3 (Science & Technology Economy)
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What Happened

  • Union Minister Ashwini Vaishnaw announced on March 7, 2026, that India has made major progress toward training 85,000 semiconductor design engineers under the Chips to Startups (C2S) programme, the country's flagship semiconductor design skilling initiative.
  • World-class Electronic Design Automation (EDA) tools from global companies — Synopsys, Cadence Design Systems, Siemens, Renesas Electronics, Ansys, and AMD — are now deployed across 315 academic institutions in India, giving students hands-on experience with industry-standard chip design software.
  • The programme aims to expand from 315 to 500 institutions, broadening the talent pipeline for India's emerging semiconductor ecosystem.
  • C2S is part of the broader India Semiconductor Mission (ISM), launched in December 2021 with a ₹76,000 crore outlay to build domestic semiconductor fabrication, assembly, testing, and design capabilities.
  • The government plans to train 85,000 VLSI and embedded systems engineers over 10 years, alongside developing 175 ASICs (Application-Specific Integrated Circuits) and 20 working System-on-Chip (SoC) prototypes.

Static Topic Bridges

Chips to Startups (C2S) Programme

Chips to Startups (C2S) is a skilling and innovation programme under the Ministry of Electronics and Information Technology (MeitY), launched as part of the India Semiconductor Mission. It targets training 85,000 engineers in VLSI (Very Large-Scale Integration) design, embedded systems, and ASIC development across academia, R&D institutions, startups, and MSMEs. The programme addresses a critical gap: while India has a large pool of engineering graduates, the country historically exported chip design talent rather than building a domestic chip industry.

  • Target outcomes (over 5-10 years): 85,000 trained engineers, 175 ASICs, 20 SoC prototypes, an IP Core repository.
  • EDA tools from Synopsys and Cadence — the global duopoly in chip design software — are now available to Indian students without commercial licensing costs, enabling real-world design experience.
  • 315 academic institutions currently participate; expansion to 500 institutions planned.
  • AICTE has introduced a new curriculum for VLSI Design & Technology and IC manufacturing across engineering colleges.

Connection to this news: The minister's announcement marks a significant milestone — 4 years into the 10-year programme, India is close to meeting its training targets, signalling that the design talent pipeline for upcoming fab projects is materialising.

India Semiconductor Mission (ISM) and the Fabrication Ecosystem

India Semiconductor Mission (ISM) was launched in December 2021 with a ₹76,000 crore outlay under MeitY. Unlike C2S (which focuses on design skills), ISM covers the full semiconductor value chain: silicon fabrication (fabs), assembly, testing, marking and packaging (ATMP), compound semiconductors, and display manufacturing. As of late 2025, 10 projects worth ₹1.60 lakh crore have been approved under ISM across 6 states, including fabs by Tata Electronics, and packaging plants by Micron Technology.

  • Tata Electronics' $10 billion fab project (in partnership with Taiwan's PSMC) in Dholera, Gujarat, is India's first planned silicon fab.
  • Micron Technology's $2.75 billion ATMP plant in Sanand, Gujarat, was the first major approved project under ISM.
  • ISM 2.0 focuses on advanced nodes and ecosystem development, with targets for 3 nm and 2 nm chip capabilities by 2035.
  • The Design Linked Incentive (DLI) scheme under ISM provides financial incentives for domestic chip design startups.

Connection to this news: C2S is the talent arm of ISM — without trained chip designers, the physical fabrication and packaging investments cannot be fully utilized. Progress in C2S is thus a prerequisite for ISM's long-term success.

VLSI Design vs. Semiconductor Fabrication: Understanding the Value Chain

The semiconductor industry consists of two distinct but interdependent segments: chip design (fabless) and chip fabrication (foundry/fab). Chip design involves creating the logical architecture and circuit layout of a chip using EDA software — a knowledge-intensive, capital-light activity. Chip fabrication involves physically etching designed circuits onto silicon wafers using highly capital-intensive cleanroom equipment (photolithography, deposition, etching). Most advanced chip design is done by US and Chinese companies (Qualcomm, Apple, Nvidia, MediaTek); most fabrication is done by TSMC (Taiwan), Samsung, and Intel.

  • India has historically been strong in chip design (Texas Instruments, Intel, Qualcomm all have large design centres in India), but had no domestic fabrication until ISM.
  • VLSI design requires mastery of Hardware Description Languages (HDL) like VHDL and Verilog, and EDA tools such as those from Synopsys and Cadence.
  • A single advanced logic chip (e.g., an Apple M-series chip) contains over 20 billion transistors, designed collaboratively by thousands of engineers.
  • Global semiconductor shortage (2020-2022) exposed strategic vulnerabilities of nations dependent on a narrow fab geography (Taiwan); ISM is partly a strategic resilience response.

Connection to this news: C2S trains engineers specifically in the chip design segment — the area where India already has competitive advantage — while ISM builds the fabrication infrastructure, with the long-term goal of India mastering both ends of the semiconductor value chain.

Key Facts & Data

  • C2S target: Train 85,000 semiconductor design engineers over 10 years.
  • Current reach: 315 institutions with world-class EDA tools (Synopsys, Cadence, Siemens, AMD, Renesas, Ansys); expanding to 500.
  • Other C2S targets: 175 ASICs, 20 SoC prototypes, an IP Core repository.
  • India Semiconductor Mission outlay: ₹76,000 crore (approved December 2021, under MeitY).
  • ISM 2.0: 10 projects worth ₹1.60 lakh crore approved across 6 states by late 2025.
  • Key fab project: Tata Electronics + PSMC (Taiwan) — $10 billion fab in Dholera, Gujarat.
  • Design Linked Incentive (DLI) scheme: supports domestic chip design startups under ISM.
  • India's goal: design and manufacture chips for 70-75% of domestic applications by 2029; top semiconductor nation by 2035.