What Happened
- Union Minister for Electronics and Information Technology Ashwini Vaishnaw announced that Semicon Mission 2.0 (India Semiconductor Mission 2.0) will focus on deep tech startups, design ecosystem creation, and equipment manufacturing — a strategic reversal from ISM 1.0's emphasis on physical fabrication and ATMP facilities
- The government allocated ₹1,000 crore for ISM 2.0 for the financial year 2026-27
- Key objectives: Create a design ecosystem enabling Indian startups to develop the next generation of chip design firms (comparable in ambition to what Qualcomm, Broadcom, or Nvidia represent globally); attract equipment manufacturers; build indigenous IP in chip architecture
- The Design Linked Incentive (DLI) scheme under ISM 1.0 has already created a foundation: approximately 67,000 semiconductor-trained engineers produced in 4 years against a 10-year target of 85,000
- ISM 2.0 explicitly inverts ISM 1.0's sequence — instead of starting with fabs (manufacturing), it prioritizes design and then connects designs to the fabs being established
Static Topic Bridges
India's Semiconductor Ecosystem — Design Strength and Manufacturing Gap
India presents a paradox in global semiconductors: it contributes approximately 20% of the world's chip design engineers and houses R&D centres of global leaders (Qualcomm, Intel, Texas Instruments, Nvidia, ARM) in cities like Bengaluru, Hyderabad, and Pune — yet it manufactures virtually no semiconductors domestically. ISM 2.0 attempts to leverage this design strength to build an indigenous chip industry.
- Fabless design model: Companies like Qualcomm, AMD, Nvidia, and Apple design chips but outsource manufacturing to foundries (TSMC, Samsung Foundry); this model requires design talent and IP but not capital-intensive fabs
- India's fabless companies: A growing number of Indian startups and companies operate in chip design — Saankhya Labs (wireless SoCs), Ola Electric's chip team, InCore Semiconductors, ScALED, and others
- Design Linked Incentive (DLI) Scheme: Provides financial support (up to ₹15 crore per company for product design), design infrastructure access (EDA tools, IP libraries), and market launch support; targets 100 domestic companies designing semiconductors over 5 years
- Electronic Design Automation (EDA) tools: Software used for chip design (Cadence, Synopsys, Mentor Graphics); India's access to advanced EDA tools has been a bottleneck; ISM 2.0 aims to ease this
- Chip-to-fab linkage: ISM 2.0 envisions Indian-designed chips being manufactured in ISM 1.0-approved fabs (Tata Electronics' Dholera fab, Micron's Sanand ATMP) — creating an integrated domestic semiconductor ecosystem
Connection to this news: Semicon 2.0 is the logical follow-on to ISM 1.0 — after securing manufacturing capacity (fabs + ATMP), the government is now building the design layer so that Indian companies can create indigenous chip IP rather than merely assembling chips designed elsewhere.
MeitY and Electronics Policy Architecture
The Ministry of Electronics and Information Technology (MeitY) is the nodal ministry for India's semiconductor and electronics policy, operating under a broader Digital India vision. Several inter-connected schemes create the policy ecosystem.
- Production Linked Incentive (PLI) for Electronics: Launched 2020-21; targets mobile phones, electronic components, IT hardware; ₹40,951 crore outlay; attracted Apple supply chain partners (Foxconn, Wistron, Pegatron)
- Scheme for Promotion of Manufacturing of Electronic Components and Semiconductors (SPECS): Provides 25% financial incentive on capital expenditure for electronics component manufacturing; addresses the component import dependence challenge
- Electronics Manufacturing Clusters (EMC 2.0): Builds plug-and-play infrastructure for electronics manufacturing — industrial sheds, power, water, roads, effluent treatment; addresses India's infrastructure gap
- India Semiconductor Mission (ISM) 1.0 (2021): ₹76,000 crore for fabs, display fabs, and ATMP; administered by DIC (Digital India Corporation) under MeitY
- ISM 2.0 (2026): ₹1,000 crore for FY27; pivots to design, equipment manufacturing, and deep tech startups; complements ISM 1.0's manufacturing push
- IESA (India Electronics & Semiconductor Association): Industry body representing the semiconductor and electronics ecosystem; interfaces with MeitY on policy
Connection to this news: Semicon 2.0's ₹1,000 crore allocation is relatively modest compared to ISM 1.0's ₹76,000 crore — reflecting that design ecosystem development requires less capital than fab construction but yields high strategic value (IP creation, export potential).
Global Chip Design Landscape — Relevance for UPSC
Understanding the global chip design-to-fab ecosystem is increasingly tested in UPSC as it intersects technology policy, industrial policy, and geopolitics.
- Global fabless leaders: Qualcomm (mobile SoCs, 5G modems), Broadcom (networking), Nvidia (GPUs, AI accelerators), AMD (CPUs/GPUs), Apple (custom ARM-based chips — M-series, A-series); none own fabs
- RISC-V architecture: An open-source instruction set architecture (ISA) developed at UC Berkeley; unlike proprietary ARM, RISC-V carries no licensing fees; India has targeted RISC-V as a platform for indigenous chip design — IIT Madras developed the Shakti processors; a national RISC-V initiative exists under MeitY
- ARM architecture: Licensed by Arm Holdings (UK; acquired by SoftBank in 2016; IPO in 2023); nearly all smartphones use ARM-based processors; India's chip design ecosystem is largely ARM-based
- 5G and AI chips: Two fastest-growing semiconductor categories; India is developing domestic 5G chipsets (Saankhya Labs has developed 5G base station chips) with strategic implications for telecom equipment self-reliance
- Chip Act competition: US, EU, Japan, and India are all incentivizing domestic chip industries — ISM 2.0 places India in global competition for chip design talent and investment
Connection to this news: ISM 2.0's ambition to build Indian Qualcomms and Nvidias requires exactly the ecosystem it is targeting — EDA access, design talent, IP support, and linkage to fabs.
Key Facts & Data
- ISM 2.0 budget allocation: ₹1,000 crore for FY 2026-27
- ISM 1.0 total outlay: ₹76,000 crore (launched December 2021)
- Semiconductor-trained engineers produced in 4 years: 67,000 (against 10-year target of 85,000)
- DLI Scheme support per company: up to ₹15 crore for product design
- DLI Scheme target: 100 domestic chip design companies over 5 years
- India's share of global chip design engineers: approximately 20%
- ISM 1.0 approved projects: 10 projects; ₹1.60 lakh crore investment across 6 states
- RISC-V initiative: IIT Madras — Shakti processor family (developed under RISE project)
- ISM administered by: Digital India Corporation (DIC) under MeitY
- Micron Sanand ATMP (first ISM project to reach production): inaugurated February 28, 2026